AMD EPYC Milan-X Processors Come With 3D V-Cache

Last Updated on November 12, 2021 by Asif Iqbal Shaik

AMD CEO Dr. Lisa Su held a virtual ‘Accelerated Data Center’ event to unveil the company’s latest EPYC Milan-X processors. These processors are meant for servers and high-end computing. EPYC Milan-X processors come with 3D-stacked L3 cache technology called ‘3D V-Cache’, which allows an additional 512MB of L3 cache on top of the current 256MB, taking the total L3 cache to 768MB per chip. AMD’s Forrest Norrod (SVP and GM for Data Center and Embedded Solutions Business Group) and Dan McNamara (SVP and GM for the Server Business Unit) were also present at the event.

AMD had teased its 3D V-Cache technology at the CES (Consumer Electronics Show) 2021, where it displayed a third-generation Ryzen prototype equipped with an additional L3 cache. The 3D V-Cache stacking technology uses a unique new hybrid bonding technique that fuses an additional 64MB of 7nm SRAM cache stacked vertically over the Ryzen compute chiplets, tripling the amount of L3 cache per chip. Moreover, its solder-less hybrid bonding technique enables a 200x higher interconnect density over 2D chiplets and a 15x higher density and 3x energy efficiency gain over micro-bump 3D packaging.

AMD claims that the 3D V-Cache stacking technology can improve gaming performance by up to 15%. However, the company is focussing on its abilities as server processors. EPYC Milan-X processors promise a 50% improvement in certain workloads. The 16-core Milan-X processors show a massive 66% performance improvement over the standard 16-core EPYC chipset.  

Microsoft’s Azure Cloud service will be the first to utilise these latest AMD processors. They have also posted synthetics benchmarks, highlighting the differences when compared to other server processors. Check the table below. 

Azure HBv3 VMs With Milan-X CPUs

Microsoft has also shared some key details for the Milan-X HBv3 VMs :

• Up to 120 AMD EPYC 7V73X CPU cores (EPYC with 3D V-cache, “Milan-X”)
• Up to 96 MB L3 cache per core (3x larger than standard Milan CPUs, and 6x larger than “Rome” CPUs)
• 350GB/s DRAM bandwidth (STREAM TRIAD), up to 1.8x amplification (~630 GB/s effective bandwidth)
• 448GB RAM
• 200Gbps HDR InfiniBand (SRIOV), Mellanox ConnectX-6 NIC with Adaptive Routing
• 2x 900GB NVMe SSD (3.5GB/s (reads) and 1.5GB/s (writes) per SSD, large block IO)
• Up to 80% higher performance for CFD workloads
• Up to 60% higher performance for EDA RTL simulation workloads
• Up to 50% higher performance for explicit finite element analysis workloads

HBv3 VMs With Milan-X Processor Sizes